1. Technical Field
This invention relates to a fabrication method of a trenched power semiconductor device, and more particularly relates to a fabrication method of a trenched power semiconductor device with a source trench.
2. Description of Related Art
On-resistance (Rds(on)) is an important factor for judging the performance of a trenched power semiconductor device, and it is helpful for reducing conductive loss. However, on-resistance is restricted by the withstanding voltage (i.e., breakdown voltage) of the trenched power semiconductor device. That is, if the thickness and the resistance of the epitaxial layer are increased to improve the withstanding voltage of the trenched power semiconductor device, the increasing of conductive loss due to the increasing of on-resistance seems unpreventable.
For the above mentioned problem, as shown in FIG. 1, U.S. Pat. No. 6,710,403 has disclosed a method of forming polysilicon-filled source trenches at the opposite sides of the gate trench for the purpose of reducing on-resistance. However, this disclosed technology needs at least three separate lithographic steps for defining the gate trench 12, the source trench 14, and the source region 16, respectively. Positioning errors between these lithographic steps may degrade the defined withstanding voltage. In addition, since a heavily doped region 18 with sufficient width should be formed adjacent to the source trench 14 for reducing contact resistance between the body and the metal layer, sufficient space should be kept between the neighboring gate trenches 12. Thus, the cell density and the on-resistance of the trenched power semiconductor device are restricted by the formation of the source trench.